1. Technical Field of the Invention
The present invention relates to semiconductor devices and methods for fabricating the same. More specifically, the present invention relates to cells of nonvolatile memory devices with floating gates and methods for fabricating the same.
2. Description of the Related Art
Memory devices like Dynamic Random Access Memory cells (DRAMs) have an advantage over Static Random Access Memory cells (SRAMs) in that they possess higher integration levels. In the DRAMs, however, memory cells should be periodically refreshed in order to prevent erasure of data stored in the cells. As a result, even in a stand-by mode, power dissipation increases. By comparison, in the case of nonvolatile memory devices like SRAMs, memory cells need not be refreshed.
FIG. 1 is a top plan view of a cell of a conventional flash memory device, which is a typical nonvolatile memory device.
FIGS. 2 and 3 are cross-sectional views of the cell of the conventional flash memory device of FIG. 1, the cross-sectional views taken along lines I—I′ and II—II′ of FIG. 1, respectively.
Referring to FIGS. 1 through 3, device isolation layers 4 are disposed at a predetermined region of a semiconductor substrate to define a plurality of active regions 3. Word lines 14, which are parallel with each other, cross over the device isolation layers 4. A floating gate 16 is located between each word line 14 and each active region 3. A tunnel oxide layer 6 is located between each floating gate 16 and each active region 3, and a gate interlayer dielectric layer 12 is between each floating gate 16 and each word line 14. Each device isolation layer 4 projects over the semiconductor substrate 2 to form sloping sidewalls where the device isolation layer 4 meets the semiconductor substrate 2.
In the conventional nonvolatile memory device, each floating gate 16 includes a lower floating gate 8 spanning adjacent device isolation layers 4 and an upper floating gate 10 partially overlapping the device isolation layer 4. Thus, a top surface and sidewalls of the upper floating gate 8 are covered with the gate interlayer dielectric layer 12. The interlayer dielectric layer 12 is typically made of an oxide-nitride-oxide (ONO) layer. The conventional nonvolatile memory device includes an upper floating gate 10 having high sidewalls in order to increase the surface contact area with the gate interlayer insulation layer 12, which is between the floating gate 16 and a control gate electrode. Thus, the coupling ratio is increased, allowing the voltages for writing and erasing data to be lowered. Unfortunately, processes may be unstable due to step coverage between a cell array region and a peripheral circuit region, and additional processes may be required to form the upper floating gate 10.